/* Copyright Statement:
*
* This software/firmware and related documentation ("MediaTek Software") are
* protected under relevant copyright laws. The information contained herein
* is confidential and proprietary to MediaTek Inc. and/or its licensors.
* Without the prior written permission of MediaTek inc. and/or its licensors,
* any reproduction, modification, use or disclosure of MediaTek Software,
* and information contained herein, in whole or in part, shall be strictly prohibited.
*/
/* MediaTek Inc. (C) 2015. All rights reserved.
*
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
*/

#ifndef __LINUX_MFD_RT5081_PMU_CHARGER_H
#define __LINUX_MFD_RT5081_PMU_CHARGER_H

#ifdef MTK_RT5081_PMU_CHARGER_SUPPORT
extern int rt5081_chg_probe(void);
#else
static inline int rt5081_chg_probe(void)
{
	return 0;
}
#endif


#define RT5081_SLAVE_ADDR		(0x34)
#define RT5081_VENDOR_ID		(0x80)

/* core control */
#define RT5081_PMU_REG_DEVINFO		(0x00)
#define RT5081_PMU_REG_CORECTRL2	(0x02)
#define RT5081_PMU_REG_HIDDENPASCODE1	(0x07)
#define RT5081_PMU_REG_HIDDENPASCODE2	(0x08)
#define RT5081_PMU_REG_HIDDENPASCODE3	(0x09)
#define RT5081_PMU_REG_HIDDENPASCODE4	(0x0A)

/* charger control */
#define RT5081_PMU_REG_CHGCTRL1		(0x11)
#define RT5081_PMU_REG_CHGCTRL2		(0x12)
#define RT5081_PMU_REG_CHGCTRL3		(0x13)
#define RT5081_PMU_REG_CHGCTRL4		(0x14)
#define RT5081_PMU_REG_CHGCTRL5		(0x15)
#define RT5081_PMU_REG_CHGCTRL6		(0x16)
#define RT5081_PMU_REG_CHGCTRL7		(0x17)
#define RT5081_PMU_REG_CHGCTRL8		(0x18)
#define RT5081_PMU_REG_CHGCTRL9		(0x19)
#define RT5081_PMU_REG_CHGCTRL10	(0x1A)
#define RT5081_PMU_REG_CHGCTRL11	(0x1B)
#define RT5081_PMU_REG_CHGCTRL12	(0x1C)
#define RT5081_PMU_REG_CHGCTRL13	(0x1D)
#define RT5081_PMU_REG_CHGCTRL14	(0x1E)
#define RT5081_PMU_REG_CHGCTRL15	(0x1F)
#define RT5081_PMU_REG_CHGCTRL16	(0x20)
#define RT5081_PMU_REG_CHGADC		(0x21)
#define RT5081_PMU_REG_DEVICETYPE	(0x22)
#define RT5081_PMU_REG_QCCTRL1		(0x23)
#define RT5081_PMU_REG_QCCTRL2		(0x24)
#define RT5081_PMU_REG_QC3P0CTRL1	(0x25)
#define RT5081_PMU_REG_QC3P0CTRL2	(0x26)
#define RT5081_PMU_REG_USBSTATUS1	(0x27)
#define RT5081_PMU_REG_QCSTATUS1	(0x28)
#define RT5081_PMU_REG_QCSTATUS2	(0x29)
#define RT5081_PMU_REG_CHGPUMP		(0x2A)
#define RT5081_PMU_REG_CHGCTRL17	(0x2B)
#define RT5081_PMU_REG_CHGCTRL18	(0x2C)
#define RT5081_PMU_REG_CHGDIRCHG1	(0x2D)
#define RT5081_PMU_REG_CHGDIRCHG2	(0x2E)
#define RT5081_PMU_REG_CHGDIRCHG3	(0x2F)
#define RT5081_PMU_REG_CHGHIDDENCTRL6	(0x35)
#define RT5081_PMU_REG_CHGHIDDENCTRL7	(0x36)
#define RT5081_PMU_REG_CHGHIDDENCTRL8	(0x37)
#define RT5081_PMU_REG_CHGHIDDENCTRL15	(0x3E)
#define RT5081_PMU_REG_CHGSTAT		(0x4A)
#define RT5081_PMU_REG_CHGNTC		(0x4B)
#define RT5081_PMU_REG_ADCDATAH		(0x4C)
#define RT5081_PMU_REG_ADCDATAL		(0x4D)
#define RT5081_PMU_REG_CHGCTRL19	(0x60)
#define RT5081_PMU_REG_OVPCTRL		(0x61)
/* status event */
#define RT5081_PMU_REG_CHGSTAT1		(0xD0)
#define RT5081_PMU_REG_CHGSTAT2		(0xD1)
#define RT5081_PMU_REG_CHGSTAT3		(0xD2)
#define RT5081_PMU_REG_CHGSTAT4		(0xD3)
#define RT5081_PMU_REG_CHGSTAT5		(0xD4)
#define RT5081_PMU_REG_CHGSTAT6		(0xD5)
#define RT5081_PMU_REG_QCSTAT		(0xD6)
#define RT5081_PMU_REG_DICHGSTAT	(0xD7)
#define RT5081_PMU_REG_OVPCTRLSTAT	(0xD8)

/* Parameter */
/* mA */
#define RT5081_ICHG_NUM		64
#define RT5081_ICHG_MIN		100
#define RT5081_ICHG_MAX		5000
#define RT5081_ICHG_STEP	100

/* mA */
#define RT5081_IEOC_NUM		16
#define RT5081_IEOC_MIN		100
#define RT5081_IEOC_MAX		850
#define RT5081_IEOC_STEP	50

/* mV */
#define RT5081_MIVR_NUM		128
#define RT5081_MIVR_MIN		3900
#define RT5081_MIVR_MAX		13400
#define RT5081_MIVR_STEP	100

/* mA */
#define RT5081_AICR_NUM		64
#define RT5081_AICR_MIN		100
#define RT5081_AICR_MAX		3250
#define RT5081_AICR_STEP	50

/* mV */
#define RT5081_BAT_VOREG_NUM	128
#define RT5081_BAT_VOREG_MIN	3900
#define RT5081_BAT_VOREG_MAX	4710
#define RT5081_BAT_VOREG_STEP	10

/* mV */
#define RT5081_BOOST_VOREG_NUM	64
#define RT5081_BOOST_VOREG_MIN	4425
#define RT5081_BOOST_VOREG_MAX	5825
#define RT5081_BOOST_VOREG_STEP	25

/* mV */
#define RT5081_VPREC_NUM	16
#define RT5081_VPREC_MIN	2000
#define RT5081_VPREC_MAX	3500
#define RT5081_VPREC_STEP	100

/* mA */
#define RT5081_IPREC_NUM	16
#define RT5081_IPREC_MIN	100
#define RT5081_IPREC_MAX	850
#define RT5081_IPREC_STEP	50

/* mV */
#define RT5081_VRECHG_NUM	4
#define RT5081_VRECHG_MIN	100
#define RT5081_VRECHG_MAX	400
#define RT5081_VRECHG_STEP	100

/* Watchdog fast-charge timer */
/* hour */
#define RT5081_WT_FC_NUM	8
#define RT5081_WT_FC_MIN	4
#define RT5081_WT_FC_MAX	20
#define RT5081_WT_FC_STEP	2

/* IR compensation */
/* mohm */
#define RT5081_IRCMP_RES_NUM	8
#define RT5081_IRCMP_RES_MIN	0
#define RT5081_IRCMP_RES_MAX	175
#define RT5081_IRCMP_RES_STEP	25

/* IR compensation maximum voltage clamp */
/* mV */
#define RT5081_IRCMP_VCLAMP_NUM		8
#define RT5081_IRCMP_VCLAMP_MIN		0
#define RT5081_IRCMP_VCLAMP_MAX		224
#define RT5081_IRCMP_VCLAMP_STEP	32

/* PE+20 voltage */
/* mV */
#define RT5081_PEP20_VOLT_NUM	30
#define RT5081_PEP20_VOLT_MIN	5500
#define RT5081_PEP20_VOLT_MAX	20000
#define RT5081_PEP20_VOLT_STEP	500

/* AICL VTH */
/* mV */
#define RT5081_AICL_VTH_NUM	8
#define RT5081_AICL_VTH_MIN	4100
#define RT5081_AICL_VTH_MAX	4800
#define RT5081_AICL_VTH_STEP	100

/* VBUSOV LVL */
#define RT5081_DC_VBUSOV_LVL_NUM	32
#define RT5081_DC_VBUSOV_LVL_MIN	3900
#define RT5081_DC_VBUSOV_LVL_MAX	7000
#define RT5081_DC_VBUSOV_LVL_STEP	100

/* IBUSOC LVL */
#define RT5081_DC_IBUSOC_LVL_NUM	8
#define RT5081_DC_IBUSOC_LVL_MIN	4000
#define RT5081_DC_IBUSOC_LVL_MAX	6500
#define RT5081_DC_IBUSOC_LVL_STEP	500

/* ADC unit/offset */
#define RT5081_ADC_UNIT_VBUS_DIV5	25 /* mV */
#define RT5081_ADC_UNIT_VBUS_DIV2	10 /* mV */
#define RT5081_ADC_UNIT_VSYS		5  /* mV */
#define RT5081_ADC_UNIT_VBAT		5  /* mV */
#define RT5081_ADC_UNIT_TS_BAT		25 /* 0.01% */
#define RT5081_ADC_UNIT_IBUS		50 /* mA */
#define RT5081_ADC_UNIT_IBAT		50 /* mA */
#define RT5081_ADC_UNIT_CHG_VDDP	5  /* mV */
#define RT5081_ADC_UNIT_TEMP_JC		2  /* degree */

#define RT5081_ADC_OFFSET_VBUS_DIV5	0 /* mV */
#define RT5081_ADC_OFFSET_VBUS_DIV2	0 /* mV */
#define RT5081_ADC_OFFSET_VSYS		0 /* mV */
#define RT5081_ADC_OFFSET_VBAT		0 /* mV */
#define RT5081_ADC_OFFSET_TS_BAT	0 /* % */
#define RT5081_ADC_OFFSET_IBUS		0 /* mA */
#define RT5081_ADC_OFFSET_IBAT		0 /* mA */
#define RT5081_ADC_OFFSET_CHG_VDDP	0 /* mV */
#define RT5081_ADC_OFFSET_TEMP_JC	(-40)  /* degree */

/* ========== CORE_CTRL2 0x02 ============ */
#define RT5081_SHIFT_CHG_RST	6
#define RT5081_MASK_CHG_RST	(1 << RT5081_SHIFT_CHG_RST)

/* ========== CHG_CTRL1 0x11 ============ */
#define RT5081_SHIFT_OPA_MODE	0
#define RT5081_SHIFT_HZ_EN	2

#define RT5081_MASK_OPA_MODE	(1 << RT5081_SHIFT_OPA_MODE)
#define RT5081_MASK_HZ_EN	(1 << RT5081_SHIFT_HZ_EN)

/* ========== CHG_CTRL2 0x12 ============ */
#define RT5081_SHIFT_CHG_EN		0
#define RT5081_SHIFT_CFO_EN		1
#define RT5081_SHIFT_IINLMTSEL		2
#define RT5081_SHIFT_TE_EN		4
#define RT5081_SHIFT_BYPASS_MODE	5

#define RT5081_MASK_CHG_EN	(1 << RT5081_SHIFT_CHG_EN)
#define RT5081_MASK_CFO_EN	(1 << RT5081_SHIFT_CFO_EN)
#define RT5081_MASK_IINLMTSEL	0x0C
#define RT5081_MASK_TE_EN	(1 << RT5081_SHIFT_TE_EN)
#define RT5081_MASK_BYPASS_MODE	(1 << RT5081_SHIFT_BYPASS_MODE)


/* ========== CHG_CTRL3 0x13 ============ */
#define RT5081_SHIFT_AICR	2
#define RT5081_SHIFT_AICR_EN	1
#define RT5081_SHIFT_ILIM_EN	0

#define RT5081_MASK_AICR	0xFC
#define RT5081_MASK_AICR_EN	(1 << RT5081_SHIFT_AICR_EN)
#define RT5081_MASK_ILIM_EN	(1 << RT5081_SHIFT_ILIM_EN)

/* ========== CHG_CTRL4 0x14 ============ */
#define RT5081_SHIFT_BAT_VOREG	1

#define RT5081_MASK_BAT_VOREG	0xFE

/* ========== CHG_CTRL5 0x15 ============ */
#define RT5081_SHIFT_BOOST_VOREG	2

#define RT5081_MASK_BOOST_VOREG		0xFC

/* ========== CHG_CTRL6 0x16 ============ */
#define RT5081_SHIFT_MIVR	1
#define RT5081_SHIFT_MIVR_EN	0

#define RT5081_MASK_MIVR	0xFE
#define RT5081_MASK_MIVR_EN	(1 << RT5081_SHIFT_MIVR_EN)

/* ========== CHG_CTRL7 0x17 ============ */
#define RT5081_SHIFT_ICHG	2

#define RT5081_MASK_ICHG	0xFC

/* ========== CHG_CTRL8 0x18 ============ */
#define RT5081_SHIFT_VPREC	4
#define RT5081_SHIFT_IPREC	0

#define RT5081_MASK_VPREC	0xF0
#define RT5081_MASK_IPREC	0x0F

/* ========== CHG_CTRL9 0x19 ============ */
#define RT5081_SHIFT_IEOC	4

#define RT5081_MASK_IEOC	0xF0

/* ========== CHG_CTRL10 0x1A ============ */
#define RT5081_SHIFT_BOOST_OC	0

#define RT5081_MASK_BOOST_OC	0x07

/* ========== CHG_CTRL11 0x1B ============ */
#define RT5081_SHIFT_VRECHG	0

#define RT5081_MASK_VRECHG	0x03

/* ========== CHG_CTRL12 0x1C ============ */
#define RT5081_SHIFT_TMR_EN	1
#define RT5081_SHIFT_WT_FC	5

#define RT5081_MASK_TMR_EN	(1 << RT5081_SHIFT_TMR_EN)
#define RT5081_MASK_WT_FC	0xE0

/* ========== CHG_CTRL13 0x1D ============ */
#define RT5081_SHIFT_WDT_EN	7

#define RT5081_MASK_WDT_EN	(1 << RT5081_SHIFT_WDT_EN)

/* ========== CHG_CTRL14 0x1E ============ */
#define RT5081_SHIFT_AICL_MEAS	7
#define RT5081_SHIFT_AICL_VTH	0

#define RT5081_MASK_AICL_MEAS	(1 << RT5081_SHIFT_AICL_MEAS)
#define RT5081_MASK_AICL_VTH	0x07

/* ========== CHG_CTRL16 0x20 ============ */
#define RT5081_SHIFT_JEITA_EN	4

#define RT5081_MASK_JEITA_EN	(1 << RT5081_SHIFT_JEITA_EN)

/* ========== CHG_ADC 0x21 ============ */
#define RT5081_SHIFT_ADC_IN_SEL	4
#define RT5081_SHIFT_ADC_START	0

#define RT5081_MASK_ADC_IN_SEL	0xF0
#define RT5081_MASK_ADC_START	(1 << RT5081_SHIFT_ADC_START)

/* ========== CHG_DEVICETYPE 0x22 ============ */
#define RT5081_SHIFT_USBCHGEN	7
#define RT5081_SHIFT_DCPSTD	2
#define RT5081_SHIFT_CDP	1
#define RT5081_SHIFT_SDP	0

#define RT5081_MASK_USBCHGEN	(1 << RT5081_SHIFT_USBCHGEN)
#define RT5081_MASK_DCPSTD	(1 << RT5081_SHIFT_DCPSTD)
#define RT5081_MASK_CDP		(1 << RT5081_SHIFT_CDP)
#define RT5081_MASK_SDP		(1 << RT5081_SHIFT_SDP)

/* ========== QCCTRL2 0x24 ============ */
#define RT5081_SHIFT_EN_DCP	1

#define RT5081_MASK_EN_DCP	(1 << RT5081_SHIFT_EN_DCP)

/* ========== CHG_PUMP 0x2A ============ */
#define RT5081_SHIFT_VG_LVL_SEL	1
#define RT5081_SHIFT_VG_EN	0

#define RT5081_MASK_VG_LVL_SEL	(1 << RT5081_SHIFT_LVL_SEL)
#define RT5081_MASK_VG_EN	(1 << RT5081_SHIFT_VG_EN)

/* ========== CHG_CTRL17 0x2B ============ */
#define RT5081_SHIFT_PUMPX_EN		7
#define RT5081_SHIFT_PUMPX_20_10	6
#define RT5081_SHIFT_PUMPX_UP_DN	5
#define RT5081_SHIFT_PUMPX_DEC		0

#define RT5081_MASK_PUMPX_EN	(1 << RT5081_SHIFT_PUMPX_EN)
#define RT5081_MASK_PUMPX_20_10	(1 << RT5081_SHIFT_PUMPX_20_10)
#define RT5081_MASK_PUMPX_UP_DN	(1 << RT5081_SHIFT_PUMPX_UP_DN)
#define RT5081_MASK_PUMPX_DEC	0x1F

/* ========== CHG_CTRL18 0x2C ============ */
#define RT5081_SHIFT_IRCMP_RES		3
#define RT5081_SHIFT_IRCMP_VCLAMP	0

#define RT5081_MASK_IRCMP_RES		0x38
#define RT5081_MASK_IRCMP_VCLAMP	0x07

/* ========== CHG_DIRCHG1 0x2D ============ */
#define RT5081_SHIFT_DC_VBATOV_EN	6
#define RT5081_SHIFT_DC_VBATOV_LVL	4
#define RT5081_SHIFT_DC_IBUSOC_EN	3
#define RT5081_SHIFT_DC_IBUSOC_LVL	0

#define RT5081_MASK_DC_VBATOV_EN	(1 << RT5081_SHIFT_DC_VBATOV_EN)
#define RT5081_MASK_DC_VBATOV_LVL	0x30
#define RT5081_MASK_DC_IBUSOC_EN	(1 << RT5081_SHIFT_DC_IBUSOC_EN)
#define RT5081_MASK_DC_IBUSOC_LVL	0x07

/* ========== CHG_DIRCHG1 0x2E ============ */
#define RT5081_SHIFT_DC_WDT	4

#define RT5081_MASK_DC_WDT	0x70

/* ========== CHG_DIRCHG2 0x2F ============ */
#define RT5081_SHIFT_DC_VBUSOV_EN	7
#define RT5081_SHIFT_DC_VBUSOV_LVL	2

#define RT5081_MASK_DC_VBUSOV_EN	(1 << RT5081_SHIFT_DC_VBUSOV_EN)
#define RT5081_MASK_DC_VBUSOV_LVL	0x7C

/* ========== CHG_STAT 0x4A ============ */
#define RT5081_SHIFT_ADC_STAT	0
#define RT5081_SHIFT_CHG_STAT	6

#define RT5081_MASK_ADC_STAT	(1 << RT5081_SHIFT_ADC_STAT)
#define RT5081_MASK_CHG_STAT	0xC0

/* ========== CHG_STAT1 0xD0 ============ */
#define RT5081_SHIFT_PWR_RDY	7
#define RT5081_SHIFT_CHG_MIVR	6
#define RT5081_SHIFT_CHG_AICR	5
#define RT5081_SHIFT_CHG_TREG	4
#define RT5081_SHIFT_DIRCHG_ON	0

#define RT5081_MASK_PWR_RDY	(1 << RT5081_SHIFT_PWR_RDY)
#define RT5081_MASK_CHG_MIVR	(1 << RT5081_SHIFT_CHG_MIVR)
#define RT5081_MASK_CHG_AICR	(1 << RT5081_SHIFT_CHG_AICR)
#define RT5081_MASK_CHG_TREG	(1 << RT5081_SHIFT_CHG_TREG)
#define RT5081_MASK_DIRCHG_ON	(1 << RT5081_SHIFT_DIRCHG_ON)

/* ========== CHG_IRQ5 0xC4 ============ */
#define RT5081_SHIFT_CHG_IEOCI		7
#define RT5081_SHIFT_CHG_TERMI		6
#define RT5081_SHIFT_CHG_RECHGI		5
#define RT5081_SHIFT_CHG_SSFINISHI	4
#define RT5081_SHIFT_CHG_WDTMRI		3
#define RT5081_SHIFT_CHGDET_DONEI	2
#define RT5081_SHIFT_CHG_ICHGMEASI	1
#define RT5081_SHIFT_CHG_AICLMEASI	0

#define RT5081_MASK_CHG_IEOCI		(1 << RT5081_SHIFT_CHG_IEOCI)
#define RT5081_MASK_CHG_TERMI		(1 << RT5081_SHIFT_CHG_TERMI)
#define RT5081_MASK_CHG_RECHGI		(1 << RT5081_SHIFT_CHG_RECHGI)
#define RT5081_MASK_CHG_SSFINISHI	(1 << RT5081_SHIFT_CHG_SSFINISHI)
#define RT5081_MASK_CHG_WDTMRI		(1 << RT5081_SHIFT_CHG_WDTMRI)
#define RT5081_MASK_CHGDET_DONEI	(1 << RT5081_SHIFT_CHGDET_DONEI)
#define RT5081_MASK_CHG_ICHGMEASI	(1 << RT5081_SHIFT_CHG_ICHGMEASI)
#define RT5081_MASK_CHG_AICLMEASI	(1 << RT5081_SHIFT_CHG_AICLMEASI)

/* ========== CHG_IRQ6 0xC5 ============ */
#define RT5081_SHIFT_BST_OLPI		7
#define RT5081_SHIFT_BST_MIDOVI		6
#define RT5081_SHIFT_BST_BATUVI		5
#define RT5081_SHIFT_PUMPX_DONEI	1
#define RT5081_SHIFT_ADC_DONEI		0

#define RT5081_MASK_BST_OLPI	(1 << RT5081_SHIFT_BST_OLPI)
#define RT5081_MASK_BST_MIDOVI	(1 << RT5081_SHIFT_BST_MIDOVI)
#define RT5081_MASK_BST_BATUVI	(1 << RT5081_SHIFT_BST_BATUVI)
#define RT5081_MASK_PUMPX_DONEI	(1 << RT5081_SHIFT_PUMPX_DONEI)
#define RT5081_MASK_ADC_DONEI	(1 << RT5081_SHIFT_ADC_DONEI)

/* ========== DPDM_IRQ 0xC6 ============ */
#define RT5081_SHIFT_DCDTI	7
#define RT5081_SHIFT_CHGDETI	6
#define RT5081_SHIFT_HVDCPDET	5
#define RT5081_SHIFT_DETACHI	1
#define RT5081_SHIFT_ATTACHI	0

#define RT5081_MASK_DCDTI	(1 << RT5081_SHIFT_DCDTI)
#define RT5081_MASK_CHGDETI	(1 << RT5081_SHIFT_CHGDETI)
#define RT5081_MASK_HVDCPDET	(1 << RT5081_SHIFT_HVDCPDET)
#define RT5081_MASK_DETACHI	(1 << RT5081_SHIFT_DETACHI)
#define RT5081_MASK_ATTACHI	(1 << RT5081_SHIFT_ATTACHI)

/* ========== CHG_STAT1 0xD0 ============ */
#define RT5081_SHIFT_MIVR_STAT	6

#define RT5081_MASK_MIVR_STAT	(1 << RT5081_SHIFT_MIVR_STAT)

/* ========== CHG_STAT2 0xD1 ============ */
#define RT5081_SHIFT_CHG_VBUSOV_STAT	7

#define RT5081_MASK_CHG_VBUSOV_STAT	(1 << RT5081_SHIFT_CHG_VBUSOV_STAT)

/* ========== CHG_STAT4 0xD3 ============ */
#define RT5081_SHIFT_CHG_TMRI_STAT	3

#define RT5081_MASK_CHG_TMRI_STAT	(1 << RT5081_SHIFT_CHG_TMRI_STAT)

/* ========== CHG_STAT5 0xD4 ============ */
#define RT5081_SHIFT_CHG_IEOCI_STAT	7

#define RT5081_MASK_CHG_IEOCI_STAT	(1 << RT5081_SHIFT_CHG_IEOCI_STAT)

/* ========== DPDM_STAT 0xD6 ============ */
#define RT5081_SHIFT_DCDTI_STAT	7

#define RT5081_MASK_DCDTI_STAT	(1 << RT5081_SHIFT_DCDTI_STAT)

/* ========== OVPCTRL_STAT 0xD8 ============ */
#define RT5081_SHIFT_OVPCTRL_UVP_D_STAT	4

#define RT5081_MASK_OVPCTRL_UVP_D_STAT	(1 << RT5081_SHIFT_OVPCTRL_UVP_D_STAT)

/* ========== CHG_MASK1 0xE0 ============ */
#define RT5081_SHIFT_CHG_MIVRM	6
#define RT5081_MASK_CHG_MIVRM	(1 << RT5081_SHIFT_CHG_MIVRM)

/* ========== CHG_MASK5 0xE4 ============ */
#define RT5081_SHIFT_CHG_IEOCM		7
#define RT5081_SHIFT_CHG_TERMM		6
#define RT5081_SHIFT_CHG_RECHGM		5
#define RT5081_SHIFT_CHG_SSFINISHM	4
#define RT5081_SHIFT_CHG_WDTMRM		3
#define RT5081_SHIFT_CHGDET_DONEM	2
#define RT5081_SHIFT_CHG_ICHGMEASM	1
#define RT5081_SHIFT_CHG_AICLMEASM	0

#define RT5081_MASK_CHG_IEOCM		(1 << RT5081_SHIFT_CHG_IEOCM)
#define RT5081_MASK_CHG_TERMM		(1 << RT5081_SHIFT_CHG_TERMM)
#define RT5081_MASK_CHG_RECHGM		(1 << RT5081_SHIFT_CHG_RECHGM)
#define RT5081_MASK_CHG_SSFINISHM	(1 << RT5081_SHIFT_CHG_SSFINISHM)
#define RT5081_MASK_CHG_WDTMRM		(1 << RT5081_SHIFT_CHG_WDTMRM)
#define RT5081_MASK_CHGDET_DONEM	(1 << RT5081_SHIFT_CHGDET_DONEM)
#define RT5081_MASK_CHG_ICHGMEASM	(1 << RT5081_SHIFT_CHG_ICHGMEASM)
#define RT5081_MASK_CHG_AICLMEASM	(1 << RT5081_SHIFT_CHG_AICLMEASM)

/* ========== CHG_MASK6 0xE5 ============ */
#define RT5081_SHIFT_BST_OLPM		7
#define RT5081_SHIFT_BST_MIDOVM		6
#define RT5081_SHIFT_BST_BATUVM		5
#define RT5081_SHIFT_PUMPX_DONEM	1
#define RT5081_SHIFT_ADC_DONEM		0

#define RT5081_MASK_BST_OLPM	(1 << RT5081_SHIFT_BST_OLPM)
#define RT5081_MASK_BST_MIDOVM	(1 << RT5081_SHIFT_BST_MIDOVM)
#define RT5081_MASK_BST_BATUVM	(1 << RT5081_SHIFT_BST_BATUVM)
#define RT5081_MASK_PUMPX_DONEM	(1 << RT5081_SHIFT_PUMPX_DONEM)
#define RT5081_MASK_ADC_DONEM	(1 << RT5081_SHIFT_ADC_DONEM)

#endif /* __LINUX_MFD_RT5081_PMU_CHARGER_H */
